Frequency synthesizers are usually provided, for example, in transmitters and receivers for wireless data transmission in order to generate radio-frequency carrier and local oscillator signals. These frequency synthesizers are normally implemented using phase locked loops.
In modern mobile radio, phase locked loops of this type are frequently subject to the requirement that they can cover a large frequency range and at the same time have a small channel separation of, for example, 200 kilohertz.
A frequency divider, which converts the signal frequency provided by an oscillator into a lower signal frequency that is compared with a reference frequency, is normally provided in the feedback path of a phase locked loop for the purpose of channel preselection.
Depending on the application, the frequency dividers which can be used in PLL synthesizers are integer frequency dividers or else those which, on average, divide by fractions.
In the case of so-called dual-modulus frequency dividers, it is possible to change over between two division ratios, one of which has been incremented by the number 1 with respect to the other. Such frequency dividers are also referred to as N/N+1 dividers. Periodically changing over between the two division ratios of the frequency divider results, on average, in the desired, non-integer division ratio.
Dual-modulus frequency dividers of this type can be used to combine the advantages of a high frequency resolution and a short stabilization time.
Frequency dividers of this type are generally also referred to as multimodulus frequency dividers. In this case, provision may be made of a multiplicity of division ratios between which it is possible to change over, for example from 128 to 255.
Since the power consumption in mobile radios such as, for example, mobile telephones or other wireless applications is to be continually reduced as data transmission rates increase, there are a multiplicity of different approaches to designing suitable programmable frequency dividers.
The document N. Foroudi et al. “CMOS High-Speed Dual-Modulus Frequency Divider for RF Frequency Synthesis”, IEEE Journal of Solid-State Circuits, Vol. 30, No. 2, February 1995 specifies a programmable divider that uses a dual-modulus prescaler. In this case, the frequency divider can be changed over between the division ratios 3 and 4 in the first frequency divider stage. A: 4 frequency divider is connected downstream as a second stage. Overall, the result is a division ratio of 16 or 15 since the division ratio “:3” is only switched on in one of four successive states of the frequency divider.
However, the architecture which has been described and applies to the frequency divider has the disadvantage that it is not possible to achieve a constant delay between the n-th input edge and the divider output edge (triggered as a result) for all values of n.
The document C. S. Vaucher et al. “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-μm CMOS Technology”, IEEE Journal of Solid-State Circuits, Vol. 35, No. 7, July 2000 describes a divider architecture that is formed from a multiplicity of :2/:3 frequency divider stages.
Given a number of n divider stages, the range of possible frequency division values m is limited to 2n≦m≦2n+1−1 in the implementation described. The smallest division ratio that can be set is also disadvantageously relatively large, particularly in the case of desired high division ratios.
The document J. Craninckx et al. “A Fully Integrated CMOS DCS-1800 Frequency Synthesizer”, IEEE Journal of Solid-State Circuits, Vol. 33, No. 12, December 1998 specifies another possible way of designing a programmable frequency divider. In this case, the frequency is actually divided by changing over the signal phases using a prescaler. In this case, the phases are preselected as a function of the desired division ratio. As with the two other approaches explained, the fact that the range of division values which can be set overall undesirably has a lower limit also applies to this approach.